Cirrus Logic CK4970x4 - Manual (Page 20)

1-13 Copyright 2012 Cirrus Logic, Inc. DS898CK7
CK49x System Description
CK49x User’s Manual
provides the recovered clock from the S/PDIF input unless it loses signal lock, in which case the
CS42528 passes the DSP clock (XTAL_OUT) that it receives on the OMCK pin.
1.3.20.3 Clock and Data Flow for HDMI or ASIO Input Data Delivery
Figure 1-7. HDMI Clocking
When the HDMI or ASIO source is selected, that device masters the system MCLK, and the input clocks
(MUXED_SCLK/MUXED_LRCLK) of the CS495xxx/CS497xxx.
The CS495xxx/CS497xxx always masters its output clocks (OUT_DAO1_SCLK/OUT_DAO1_LRCLK).
Note:
MUXED_MCLK is the clock signal that is driven by the HDMI source.
Table 1-4. HDMI Clocking
Clock Name Clock Master Source Clock Driver Clock Frequency
MUXED_MCLK HDMI/ASIO Source HDMI/ASIO Source
256*S/PDIF Fs
(e.g. 12.288 MHz for 48 kHz)
DAI1_SCLK MUXED_MCLK HDMI/ASIO Source 64*Input Fs (default)
DAI1_LRCLK MUXED_MCLK HDMI/ASIO Source Input Fs
OUT_DAO1_SCLK MUXED_MCLK CS495xxx/CS497xxx 64*Output Fs (default)
OUT_DAO1_LRCLK MUXED_MCLK CS495xxx/CS497xxx 1*Input Fs (default)
CS4953x4
HDMI RX /
ASIO Input
DAI1
_S
CL
K
OUT_DAO1_SCLK
OUT_DAO1_LRCLK
DAI1
_LRCL
K
MU
XE
D
_DA
I[4:0
]
DSP_DA0[3:0]
XMTA
S/PDIF
OU
T
MUXED_BUF_MCLK
DAI DAO
SDIN
CS42528
XT
AL
_O
U
T
CS2000
S/PDIF
RX