Cirrus Logic CK4970x4 - Manual (Page 40)

Programming the DSP on the CK49x Evaluation Board
CK49x User’s Manual
DS898CK7 Copyright 2012 Cirrus Logic, Inc 4-6
4.3.4 DAI Input
Each available audio source for the board is shown as a block connected to the DAI port of the CK49x as
illustrated in Figure 4-8 . Right-clicking any of the sources and selecting Device Properties, produces the
DAI Properties
dialog.
Figure 4-8. CK49x DAI Input Properties
This dialog allows the user to set the following parameters for the CK49x:
• SCLK polarity - Rising edge / Falling edge
• LRCLK polarity - Channel 0 low / Channel 0 high
• Channel Mode - SPDIF on pin 4 / SPDIF on pin 0
• Temperature Grade - CK49xs are populated with commercial-grade chips by default
• Ref Clock - Set to the frequency of the crystal driving the CS49353xx (Y1). This is the reference
clock is used to determine the clock dividers needed to derive Fs in ADC-only applications. If this
number changes, then all dividers for LRCLK/SCLK will change by the same ratio (e.g.
@24.576 MHz MCLK/512 = 1Fs = LRCLK, @12.288 MHz MCLK/256 = 1Fs = LRCLK)