Document Outline

• Crystal lan™ cs8900a ethernet controller technical reference manual
• Schematic Checklist
• software checklist
• INTRODUCTION TO CS8900A TECHNICAL REFERENCE MANUAL
  • Figure 1. Hardware Application Summary
  • Figure 2. Software Application Summary
• HARDWARE DESIGN
• CS8900A: Connecting to NON-ISA bus SYSTEMS
  • The CS8900A Architecture
    • ISA Bus
    • CS8900A in I/O Mode
    • CS8900A in Memory Mode
    • DMA Interface of the CS8900A
  • Selection of I/O, Memory and DMA Modes
  • Design Example: CS8900A Interface to MC68302
    • Figure 3. Connection of CS8900A to MC68302
    • Address Generation
    • Read and Write Signals
    • SBHE Signal
    • Other Control Signals
    • Status Signals from CS8900A
  • Databus (SD[0:15]) Connection
  • Checklist for Signal Connections to the CS8900A
  • EEPROM Optional
  • Design Example: CS8900A Interface to Cirrus Logic CL-PS7211
    • Figure 4. CS8900A Interface to Cirrus Logic CL-PS7211
  • Design Example: CS8900A Interface to Hitachi SH3
    • Figure 5. CS8900A Interface to Hitachi SH3
  • Summary
• Ethernet Hardware Design for Embedded Systems and Motherboards
  • General Description
  • Board Design Considerations
    • Crystal Oscillator
    • ISA Bus Interface
    • Figure 6. Placement of Components, Top Side
    • Figure 7. Placement of Components, Solder Side
    • External Decode Logic
    • EEPROM
    • LEDs
    • 10BASE-T Interface
    • 10BASE-2 and AUI Interfaces
  • Logic Schematics
    • Figure 8. 10BASE-T Schematic 3.3V
    • Figure 9. Overall Schematic
  • Component Placement and Signal Routing
    • Figure 10. 10BASE-T Schematic 5V
    • Figure 11. Decoupling Capacitors Schematic
  • Bill of Material
    • Table 1. CS8900A Design Bill of Materials
• Low Cost Ethernet Combo Card Reference Design: CRD8900
  • General Description
  • Board Design
    • Figure 12. Placement of Components
    • Figure 13. CS8900A Schematic (Combo Card Application)
    • Figure 14. Power Supply Decoupling Schematic
    • Figure 15. Boot PROM Schematic
    • Figure 16. AUI Schematic
    • Figure 17. 10BASE-2 Schematic
    • Figure 18. PAL Decode of LA[20-23]
    • Crystal Oscillator
    • ISA Bus Interface
    • External Decode Logic
    • EEPROM
    • Socket for Optional Boot PROM
    • Table 2. BootPROM Descriptions Stored in CS8900A PacketPage
    • LEDs
    • 10BASE-T Interface
    • AUI Interface
    • 10BASE-2 Interface
  • Logic Schematics
  • Component Placement and Routing of Signals
    • Figure 19. CRD8900 Top-Side Routing
    • Figure 20. CRD8900 Bottom Side Routing
  • Bill of Material
    • Table 3. CS8900A COMBO Card Reference Design Bill of Materials
  • Addressing the CS8900A: I/O Mode, Memory Mode
    • I/O Mode
    • Memory Mode
      • Lower Memory Mode
      • Extended Memory Mode
      • Figure 21. PAL Decode of LA[20-23]
      • Figure 22. Typical CS8900A Ethernet Connection
      • Figure 23. PAL Program
  • Layout Considerations for the CS8900A
    • General Guidelines
      • Figure 24. General placement on an ISA adapter card
    • Power Supply Connections
      • Two Layered Printed Circuit Board (PCB)
      • Multi-layered Printed Circuit Board
      • Figure 25. Placement of Components, Top Side
      • Figure 26. Placement of Components, Solder Side
      • Figure 27. Component (top) side of four-layer board
      • Figure 28. +5V Plane of four-layer board
      • Figure 29. Ground Plane of four-layer board
      • Figure 30. Solder side (bottom) of four-layer board
      • Figure 31. Placement of Decoupling Capacitor (Bottom side, under CS8900A)
      • Figure 32. Routing of Decoupling Capacitor (Top side, component side)
    • Routing of the Digital Signals
    • Routing of the Analog Signals
      • Figure 33. 10BASE-T Transit Layout Details
      • Figure 34. 10BASE-T Receive Layout Details
• Recommended Magnetics for the CS8900A
  • Table 4. Partial List of Recommended AUI Transformers
  • Table 5. Partial list of Recommended 10BASE-T Transformers
  • Table 6. Transformer Vendors
• JUMPERLESS DESIGN
  • Serial EEPROM
    • Reset Configuration Block
      • Table 7. EEPROM Reset Configuration Block
    • Driver Configuration Information
    • Format of Driver Configuration Block
      • Table 8. EEPROM Driver Configuration Block
    • Maintaining EEPROM Information
  • Embedded Designs
    • BIOS-Based Design Considerations
    • Driver Interface with BIOS-Based Configuration
      • Table 9. Format of Driver Configuration Block in BIOS space
• Obtaining IEEE Addresses
• DEVICE DRIVERS AND SETUP/INSTALLATION SOFTWARE
  • DOS Setup and Installation Utility
    • Installation Procedure
• CONTACTING CUSTOMER SUPPORT AT Cirrus
  • Cirrus Web Site