BNC 6040 - Manual (Page 41)

41
SECTION 3
THEORY OF OPERATION
General
PULSE GENERATOR
Figure 3-1 shows a simplified block diagram of the timing circuits. There are four main functional
groupings: Rep-Rate Generator. External Trigger Circuit, Delay Circuit and Width Circuit. A high
speed multiplexer selects either the output of the External Trigger Circuit or one of frequencies
available from the Rep Rate Generator. The selected signal generates a TRIG OUT pulse and triggers
the Delay and width are digitally programmable with 1 ns resolution. The entire signal path from either
circuits involves approximately 20 IC gates. Excellent time coherence (-25 ps rms) is advanced
through careful layout and the use of high speed ECL devices.
The top rows of blocks represent a frequency synthesizer employing a phase locked loop (PLL) to
insure that crystal accuracy is maintained for all rep rates. The dashes (blocks) indicate CMOS
counters that are located on the Microprocessor board. By programming the 16-bit divides in the PLL
feedback path as well as the 4-bit and two 16-bit dividers outside the loop, all of the required
frequencies are obtained.
When the external Trigger Circuit is used, the multiplexer sselects the line from the fast comparator.
The x2 attenuator at the input provides a wideband low VSWR termination for the external triggers. An
8-bit DAC plus a polarity bit provides 0.2% resolution (20 mV/step) for the trigger threshold level. When
solid triggering occurs, an LED indicator lights.
The two remaining circuits (Delay and Width) are essentially identical. An input pulse starts a 100 MHz
oscillator running. The 4-bit (÷16) counter begins to count the oscillator pulses. When the programmed
Width is reached, the trailing edge of the (previously started) output pulse returns to ground and the
entire cycle can be repeated almost immediately. DRIVE, an ECL version of the PULSE OUT output is
sent to the plug-in module.
SOFTWARE AND MICROPROCESOR
The model 6040 is based on the Intel 80C31 family of microprocessors (see Figure 3-2). This
microprocessor, optimized for imbedded controller applications such as the BNC 6040, is very efficient
at bit control, has a built-in serial I/O and baud rate control, and supports a six-level interrupt system.
Programs developed for the 6040 are written in the C language using a cross-assembler. Some low
level routines are coded in assembly for speed and efficiency.
The software has a timer interrupt for the keypad interface, as well as interrupt driven GPIB and RS-
232 routines. The timer interrupt occurs at intervals of 50ms. This allows optimal keypad detection while
minimizing interruptions of other software tasks.