BNC 6040 - Manual (Page 50)

50
THEORY OF OPERATION
The presettable counters, Z16-A and Z16-B, are enabled by the signals, DCNT24 and DCNT220,
respectively. These come from port C of the PPI Z22. They are set by the microprocessor according to
the Delay setting.
The LDCLK signal is used when the counters are loaded with a new value. This comes from port C of
the PPI, Z22.
The DHLDOFF signal is used to prevent the ECL delay circuitry from initiating a new delay cycle during
the reloading of Z16 at the end of a delay cycle.
The DTTLEN signal allows the ECL circuitry to generate the DTTLCK signal.
The DTTLCOIN signal indicates that the CMOS count chain has reached 0 (counted down).
CMOS Width Circuit (Schematic 6040-33, Sheet 7)
The width counter circuitry is essentially identical to the description of the delay counters.
The CMOS width circuit is similar to the delay circuit. In the width circuitry Z20 is the LSI counter, and
signals that began with a 'D' begin with a ‘W’.
Z20 is a 82C54 that contains three user configurable 16-bit counters. These are configured as two
programable counters, and a fixed prescaler. The CMOS count can be up to four bytes wide. The
Z20-A counter is loaded with two least significant bytes and is clocked from the WTTLCK signal, at a
frequency of 6.25 MHz (a period of 160 ns).
The Z20-B counter is loaded with the remaining two high order bytes and is clocked by the output of the
prescaler Z20-C. The prescaler divides the 6.25 MHz WTTLCK signal by 65536
(2
16
) producing a frequency of 95.367 Hz.
The presettable counters, Z20-A and Z20-B, are enabled by the signals, WCNT24 and WCNT220.
respectively. These come from port C of the PPI Z22 and are set by the microprocessor according to
the Width setting.
The LWCLK signal is used when the counters are loaded with a new value from port C of the PPI Z22.
The WHLWOFF signal is used to prevent the ECL width circuitry from initiating a new width cycle
during the reloading of Z20 at the end of a width cycle.
The WTTLEN signal allows the ECL circuitry to generate the WTTLCK signal.
The WTTLCOIN signal indicates that the CMOS count chain has reached 0 (counted down).