BNC 6040 - Manual (Page 44)

44
THEORY OF OPERATION
At the start of the width timing cycle Z6-15 transmits a rising edge to the clock input of Z28 via DL2.
This initiates the width output. The electrical length of DL2 is equivalent to the sum of the propagation
time through Z19, Z20, Z21 and Z29 when the data set in the 1 ns decade is zero. At the end of the
width timing cycle. Z26 transmits this edge through the 1 ns circuits (Z29 and Z20) the multiplexer (Z21)
and the pulse shaper (Z29-14) to Z28-12 to end the width cycle. The outputs of Z28 supply both the
plug-in and the output amplifier with a width signal.
Microprocessor Board (Schematic 6040-33)
CPU and Interface (Schematic 6040-33, Sheet 1)
Z8, is an Intel 80C31 Microprocessor. Since it has no internal program memory, all program memory is
contained in an external EPROM. The output of Zll, a 10 MHz crystal oscillator (described later), is
buffered by Z13C and drives Z8-19. It also drives the CMOS counter circuits.
Port 0 on Z8 is used as both a bidirectional data bus and lower bit address latch control. The
bidirectional data buffer Z14, points away from the microprocessor except during a data or I/O read.
Port 0 is also connected to Z15. an 8-bit latch used for demultiplexing AD0-AD7. The lower eight bits of
the address are always placed on the bus during the first portion of an external memory read or write
cycle. Latching of the address bits occurs when ALE (Address Latch Enable) on Z8-30 (on its trailing
edge) goes from high to low. Also during this first cycle A8-A15 are presented to an output buffer for the
upper eight address lines.
External 4.7 k pull-up resistors are required on the PO port. Note that the buffered DATA bus actually
contains the both the multiplexed address and data information though only the data is recovered by
other chips on the logic board. The special "quiet bus", however, re-decodes the multiplexed
address/data bus. This is discussed in greater detail in the Module Interface description (sheet 9).
An internal serial port for communication to a three-wire DCE device is provided via the CMOS to RS-
232C translation devices. Z3 and Z5 are the RS-232C bus driver and receiver. Note that Z3 is the only
device requiring -12 V and +12 V. This is necessary to produce the proper voltage swing for the RS-
232C standard. Baud rates of 300-1200 are supported, and data is fixed at eight bits, no parity.
Bus and External Memory Control Lines:
Memory is divided into two sections identified as Code and Data. Hardware I/O is mapped in the Data
space.
Code (program memory as opposed to data memory) is read by the microcomputer when
PSEN*, Z8-29, goes low (true). This signal, combined with A0-A15, allows 2
16 or 65,536 directly
addressable program memory locations. Program memory is stored in Z17 (sheet 2).
Data (Read/Write memory or RAM) is read and latched by the microprocessor when RD*, Z8-17, goes
from low (true) to high (false). While the microprocessor can theoretically address 65,536 data spaces,
only 8192 locations (8K) are used for the RAM. I/O (hardware used to control or sense the 6040) is also
mapped into the Data space. This includes the module and timing board control circuits.