BNC 6040 - Manual (Page 51)

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THEORY OF OPERATION
GPIB Interface (Schematic 6040-33, Sheet 8)
Z35's CS7 (chip select 7) enters Z4 on pin 3 and in conjunction with AO-A3 select internal registers on
the TMS9914 bus controller. The RD* must be inverted to accommodate the unusual positive-true
DBIN (data bus in) signal.
Z6 is used to divide the 10 MHz logic board oscillator which is output to Z4's clock input.
Z1 and Z2 are standard 75161 and 75160 interface driver chips normally used with the 9914. They go
to the 26-pin connector which in turn is connected to the 24-pin GPIB connector mounted on the back
of the 6040.
Module Interface (Schematic 6040-33, Sheet 9)
The quiet bus, J8, is a specially designed bus to minimize interference caused by normal CPU bus
noise. J8 provides the communication path to the plug-in modules. (See Table 3-1.)
The microprocessor controls the plug-in module via the 40-pin connector, J8. There are four interface
control lines QRD, QWR, QALE, PLUGIN. QRD and QWR are used to control the direction of data
(read from or write to the module). QALE is used for demultiplexing the QAD multiplexed data/address
lines. PLUGIN enables the module data transaction.
The data/address bus consists of five address lines and eight multiplexed data/address lines. This
allows an access of 8K bytes of memory or I/O in the module.
The power for the module is also supplied via J8, but the cable is cut and fitted with a second 16-pin
DIP connector which is routed to the power supply (PCB 6040-1).
PLL and Rate Limiter (Schematic 6040-33, Sheet 10)
The 20-pin connector, J9, is used for all dynamic signals between the microprocessor board (PCB
6040-3) and the timing board (PCB 6040-2). (See Table 3-2.)