BNC 6040 - Manual (Page 49)

49
THEORY OF OPERATION
Software normally sets port A to all zeroes. During the primary 50 ms operating system timer tick
interrupt, the lower half of port C is tested to see if any bits are low. A bit will be low if any key is
pressed because the 4.7 k row resistor is pulled low by a connection through the keypad switch.
Once a key is pressed, software selectively scans through the columns one by one testing until the
unique combination of a row and column is identified.
LED and LCD Display Interface:
Port B of Z33 is connected to both the data bus of the LCD display and Z30 an octal latch and port
driver for the eight LEDs. Strobing of data to control the LEDs is accomplished by bit 4 on Port C.
Strobing of data to control the LCD is by strobing bits 5. 6. and 7 of this same port.
ECL Interface (Schematic 6040-33, Sheet 5)
The microprocessor uses a pair of 82C55 Programmable Peripheral Interfaces (PPIs) to control the
timing board (PCB 6040-2). The PPIs, Z19 and Z22, control the timing board via the 40-pin connector
J6. Each PPI has three I/O ports which are one byte wide. All of the ports are for output control except
Z22, port C's lower four bits.
Z19 controls the 1 ns and 10 ns timing decades. Port A controls the delay, while port B controls the
width. Port C is used for resetting the CMOS counters and to reset the overlap detector on the timing
board.
Z22 controls the trigger circuits, enables the CMOS Timing counters, and monitors the status of
hardware on the Timing board. Port A has the SEL A,B, and C lines, that are used in the rep-rate
generator. FRQEN, RALMT, and DBLPLS enable the trigger generator, the rate limit circuitry, and allow
double pulses. TRGSL and TRGPOL determine the slope and polarity for the External Trigger circuitry.
Port B sets the External Trigger threshold DAC. The lower four bits of port C allows the microprocessor
to monitor when a timing cycle is in progress (DWPROG), if the PLL is out of lock (PLLK), if a timing
cycle error has occurred (OVRLAP). and if an external trigger has been recognized by the discriminator
(TGR'D). Port C's upper four bits is used to enable the CMOS timing count chain.
CMOS Delay Circuit (Schematic 6040-33. Sheet 6)
This circuit augments the high speed ECL delay circuitry. It extends the delay from 159 ns to more than
100 s. This is done by utilizing a single LSI counter and four SSI ICs.
Z16 contains three user configurable 16-bit counters, configured as two programable counters and a
fixed prescaler. The CMOS count can be up to four bytes wide. The Z16-A counter is loaded with two
least significant bytes and is clocked from the DTTLCK signal, at a frequency of 6.25 MHz (a period of
160 ns).
The Z16-B counter is loaded with the remaining two high order bytes and is clocked by the output of the
prescaler, Z16-C. The prescaler devides the 6.25 MHz DTTLCK signal by 65536 (2 to the 16)
producing a frequency of 95.367 Hz.