BNC 6040 - Manual (Page 43)

43
THEORY OF OPERATION
The external trigger circuit consists of Z4, Z7, Z13, Z22 and Q3, Z4 (a DAC) is supplied data from the
microprocessor board and with the aid of Z7 sets the input trigger level. Q3 when activated inverts the
level polarity. Z13 is a high speed comparator and is used as the input sensing device. Three sections
of Z22 are used to select the slope of the incoming signal.
The fourth section of Z22 is used to detect the presence of a successful input trigger. lengthen the
pulse (if necessary) and flash the trigger indicator.
Z8-3 is used to lock out a signal from Z15 and thus prevent triggering of the 6040 when required. The
upper portion of Z23 is used to shorten (typically 3 ns) any pulse on its clock input for timing purposes.
Z30-4 is used to stretch the pulse for use by the CMOS circuits on the microprocessor board.
Delay Circuit (Schematic 6040-32 Sheet 2)
The delay trigger from sheet 1 starts the delay cycle when Z25 is enabled Z25 pin 10 is the trigger input
and pin 11 is a disable from the CMOS circuitry that prevents additional triggers while the CMOS
circuitry is being loaded with data. The input on pin 9 performs a similar function until coincidence is
reached (the end of the delay cycle.)
Z16-15 is a delay line oscillator that runs at 100 MHz and is enabled by Z18-14. When Z18-12 is set by
Z25 the oscillator is enabled and supplies clock pulses to Z18-11 and Z6 (a binary counter) until both
CMOS and ECL coincidence are present at the same time. When this condition is met there is one
more clock pulse which loads the counter returns Z18 to its original state and disables the oscillator.
Z25-7 is used to proved two signals: one to the TRIG OUT amplifies and the other to the width circuit at
the beginning of delay in the Double pulse mode only. The Z18-14 output in addition to controlling the
oscillator, also provides a signal to the 1 ns delay circuit (Z9 and Z17). Z17 determines the 0 to 1 ns
increments.
Z9 determines the 2, 4, 6 or 8 ns delay as selected by Z10. The output of Z10 buffered and inverted by
Z17-15 and the trailing edge of the delay pulse is detected by Z18-6 which then generates a short pulse
(3 ns typical). This pulse is the trigger for the width circuit. Z27 is used to detect the presence of a
trigger during a cycle and fire the overlap indicator via the microprocessor
Width Circuit (Schematic 6040-32, Sheet 3)
The width trigger is inverted by Z26 (when enabled) and sets Z28 starting the width timing cycle Z26-10
disables the gate when data is being loaded into the CMOS circuits. Z26-11 disables the gate when a
trigger signal sets Z28 and prevents the acceptance of any additional triggers until the width timing
cycle is completed.
When set by the trigger the Z28-3 output enables the 100 MHz delay line oscillator (Z31-15). The
output of Z31 drives both Z28 and Z32 (a binary counter) with clock pulses. The carry output of Z32
supplies the CMOS circuits with clock pulses via Z29-2 and Z11-13. Z32 continues to count until both
CMOS and ECL coincidence is reached. The next clock pulse returns Z28 to its original state. In
addition this extra clock pulse reloads data into Z32.