BNC 6040 - Manual (Page 42)

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THEORY OF OPERATION
When power is first applied the software determines if a plug-in module is present and configures the
front panel user interface as necessary. This includes enabling or disabling the selection of certain
parameters. Modes, and Timing States, and the limiting of parameters to boundaries as specified by
the module.
The microprocessor has 64K bytes of code memory, and a separate 64 K bytes of data memory. Code
is accessed when the CODE SELECT line (PSEN) is asserted. In the 6040, the hardware control is
realized by “memory mapping” the interface ICs into the data memory space.
The microprocessor is mapped into 8K bytes of RAM which is used for temporary values and the stack.
The module is mapped into 8K bytes of memory. There is a special bus interface designed to minimize
bus induced noise in the module.
The CMOS timers are mapped into a 2K byte segment of memory. There are total of four LSI counters,
Each having three 16-bit timers, for a total of 12 timers. These are used to augment the range of the
ECL circuitry and interface via the 20-pin connector 19.
The ECL I/O is mapped into a 512-byte segment of memory. This allows 32 bits to control circuitry and
four bits to monitor the timing hardware. These interface to the timing board via the 40-pin connector,
J6.
The front panel control is mapped into a 256-byte segment. This notifies (interrupts) the processor
when the 6040 has been addressed (as set by the GPIB key parameter, 488 Add) via the GPIB.
The RS-232 takes advantage of he 80C31’s internal serial port. The processor’s circuitry interrupts the
processor when the RS-232 port is active.
CIRCUIT DESCRIPTION
Simplified Interconnection Diagram
This diagram depicts the signal flow between circuit boards in the 6040, as well as inputs and outputs
to and from the front panel, rear panel and plug-in module. The printed circuit boards are shown with
their assigned number. Such as PCB 6040-1 for the Power Supply Board. The schematic number for
each board is also shown.
Timing Board (Schematic 6040-32)
Rep-Rate Generator and External Trigger Circuit (Schematic 6040-32, Sheet 1)
The rep-rate generator schematic consists of Z1, Z2 and Z5, Z8 buffers the signal from Z5 and drives
Z14 (a binary divider) and Z15 ( a multiplexer). The external trigger circuit also supplies a signal to the
multiplexer.