Characteristics of the sync input, Overview, Dars (digital audio reference signal) – NTi Audio Digirator DR2 User Manual

Page 13

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13

Overview

Characteristics of the SYNC input

The sampling frequency of the Digirator can be synchronized
and locked to external devices. In order to do this, the sync
signal is connected to the universal sync input circuitry via a
female XLR connector to the DR2. An adaptor for connecting
a BNC cable to the XLR input is also included as a standard ac-
cessory item with the DR2.

Supported sync / clock formats

The Digirator recognizes clock sources automatically as they
are connected. There is no need for a manual selection of the
sync format. The following formats are supported:

•  AES3 / DARS  20 kHz to 216 kHz (continuous)
•  Word Clock 

32 kHz (+/- 100 ppm)

44.1, 48 kHz (x1, x2 , x4) (+/- 100 ppm)

•  Black Burst 

PAL (25 Hz) and NTSC (29.97 Hz)

fs = 48 kHz

1

3

2

AES / EBU

XLR - 110

AES3-id

S/PDIF

RCA - 75

1

3

2

110

75

75

Word Clock,
Blackburst
Video

AES3,
DARS

SYNC IN

XLR - 110

Ω,

75

Ω, High-Z

Clock
Processing

Digital Audio
Transmitter

fs

WAVE

DEFAULT

FOLDER2

...

• Signal1.wav

• Signal2.wav

• ...

• Signal1.wav

• Signal2.wav

• ...

Input impedance

AES3 as well as Word Clock signals are separated by an electri-
cally isolated transformer terminated with the nominal imped-
ances of 110 ohm or 75 ohm. But Hi-Z mode is also supported,
allowing trial operation of the DR2 in parallel with other de-
vices.

Jitter suppression

The extracted sampling frequency is fed into a clock recovery
stage with high jitter attenuation. This ensures stable and opti-
mized signals at the DR2 output. With input sampling frequen-
cies that deviate more than 100 ppm from the AES standard
sampling frequencies, no clock recovery will be executed. Un-
der special circumstances this might lead to suboptimal stabil-
ity of the output signal .

DARS (Digital Audio Reference Signal)

... is an AES3 Signal, intended for syn-
chronizing equipment. Its channel status
data are marked accordingly by setting the
DARS Bits.

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