Rockwell Automation 1747-PT1, D1747NP002 Hand-Held Terminal User Manual
Page 259
Instructions
Chapter 18
I/O Message and Communication
18–13
Example 3
Operation Notes
The timeout bit is latched (rung 4) after a period of 2 seconds. This
clears the message instruction from processor control on the next
scan. The message instruction is then re-enabled for a second attempt
at transmission. After 5 attempts, O:1/0 is latched.
A successful attempt at transmission resets the counter, unlatches O:1/0,
and unlatches B3/1.
END
0
[LBL]
1
(EN)
(DN)
(ER)
MSG
READ/WRITE MESSAGE
Read/write
WRITE
Target Device
500CPU
Control Block
N7:0
Control Block Length
7
]/[
T4:0
DN
(EN)
(DN)
TON
TIMER ON DELAY
Timer
T4:0
Time Base
0.01
Preset
200
Accum
0
] [
B3
1
(CU)
(DN)
CTU
COUNT UP
Counter
C5:0
Preset
5
Accum
0
(JMP)
1
N7:0
8
(RES)
C5:0
(L)
N7:0
(U)
O:1.0
0
(U)
B3
1
(L)
O:1.0
0
] [
B3
1
] [
T4:0
DN
] [
C5:0
DN
] [
N7:0
13*
1
2
3
5
6
7
* MSG instruction
status bits:
8 = TO
13 = DN
15 = EN
2–second timer. Each
attempt at transmission has a
2–second duration.
Counter allows 5 attempts.
N7:0/8 is the message
instruction timeout bit.
Clear the control word and
jump back to rung 0 for
another attempt.
The fifth attempt latches
O:1/0.
B3/1 is latched to initiate
the message instruction.
] [
T4:0
DN
4
] [
8
CLR
CLEAR
DEST
N7:0
0