Rockwell Automation T8110B/T8110 Trusted TMR Processor - Manual (Page 8)

Trusted
TM
TMR Processor T8110B/T8110
Issue 18 Feb 08 PD-T8110B/T8110 8
1. Description
Figure 1 Module Architecture
1.1. Overview
The Trusted TM TMR Processor is a fault tolerant design based on a TMR architecture arranged in a
lock-step configuration. Figure 1 shows, in simplified terms, the basic structure of the Trusted TM TMR
Processor module.
The module contains three processor fault containment regions (FCR), each containing a Motorola
Power PC series processor and its associated memory (EPROM, DRAM, Flash ROM, and NVRAM),
memory mapped I/O, voter and glue logic circuits. Each processor FCR has voted two-out-of-three (2-
oo-3) read access to the other two processor FCRs memory systems to eliminate divergent operation
The module’s three processors store and execute the application program, scan and update the I/O
modules and detect system faults. Each processor executes the application program independently,
but in lock-step synchronisation with the other two. Should one of the processors diverge, additional
mechanisms allow the failed processor to re-synchronise with the other two.
Each processor has an interface with the Inter-Module Bus which consists of an input voter,
discrepancy detector logic, memory and an output driver. The output of each processor is connected
by the module connector to a different channel of the triplicated Inter-Module Bus.
Communication between the Trusted TM TMR Processor and modules in other chassis is via either a
Trusted TM Interface module, such as the Trusted TM TMR Interface to a Regent+Plus I/O chassis, or an
Expander Interface to a Expander chassis.