Achronix Speedster22i User Macro Guide - Manual (Page 200)

Multipliers BMULT28X28
Speedster22i Macro Cell Library Achronix Semiconductor Proprietary PAGE 183
BMULT28X28
28

28 Signed Multiplier
din0[27:0]
din1[27:0]
dout[55:0]
BMULT28X28
BMULT28X28 implements a signed 28

28 multiplier that multiplies two signed (two’s
complement) 28‐bit inputs for produce a 56‐bit signed product.
Table 7-6: Pin Description
Name Type Description
din0[27:0],
din1[27:0]
Signed (two’s complement) 28-bit multiplier inputs. Bit 0 is the LSB.
dout[55:0]
Signed (two’s complement) 56-bit product. The value on dout is the
product of din0[27:0] and din1[27:0]. dout[0] is the LSB.
Verilog Instantiation Template
BMULT28x28 instance_name
(.dout(user_out[55:0]),.din0(user_in1[27:0]),.din1(user_in0[27:0]));
VHDL Instantiation Template
------------- ACHRONIX LIBRARY ------------
library speedster22i;
use speedster22i.components.all;
------------- DONE ACHRONIX LIBRARY ---------
-- Component Instantiation
BMULT28x28_instance_name : BMULT28x28
port map (dout => user_out,
din0 => user_in0,
din1 => user_in1);
Figure 7-3: Logic Symbol
input
output