Achronix Speedster22i User Macro Guide - Manual (Page 68)

Registers DFFE
Speedster22i Macro Cell Library Achronix Semiconductor Proprietary PAGE 52
Verilog Instantiation Template
DFFE #(.init(1’b0))
instance_name
(.q(user_out),
.d(user_din),
.ce(user_clock_enable),
.ck(user_clock));
VHDL Instantiation Template
------------- ACHRONIX LIBRARY ------------
library speedster22i;
use speedster22i.components.all;
------------- DONE ACHRONIX LIBRARY ---------
-- Component Instantiation
DFFE_instance_name : DFFE
generic map ( init => ‘0’)
port map (q => user_out,
d => user_din,
ce => user_clock_enable,
ck => user_clock);