Achronix Speedster22i User Macro Guide - Manual (Page 222)

PLL/DLL Clock Generators ACX_CLKGEN
Speedster Macro Cell Library www.achronix.com PAGE 205
VHDL Instantiation Template
------------- ACHRONIX LIBRARY ------------
library speedster22i;
use speedster22i.components.all;
------------- DONE ACHRONIX LIBRARY ---------
--Component instantiation
ACX_CLKGEN_instance_name
generic map (
clkdiv => "000001",
intfb => "0" ,
phaseinc_sat => "0",
clkmult => X"00",
synthmode => "0",
frac_div_ctrl => X"0000",
clkouten_mode => "0",
pll_user_reset_en => "0",
pll_user_outrst_en => "0",
pll_user_csrrst_en => "0",
bypass0 => "0",
outdiv0 => "000100",
en_phase0 => "1",
static_phase0 => "000",
dyn_phase0 => "0",
byp_clkdiv0 => "1",
high_cnt0 => "0000000000",
low_cnt0 => "0000000000",
half_cycle0 => "0",
clken_out0 => "1",
bypass1 => "0",
outdiv1 => "000100",
en_phase1 => "1",
static_phase1 => "000",
dyn_phase1 => "0",
byp_clkdiv1 => "1",
high_cnt1 => "0000000000",
low_cnt1 => "0000000000",
half_cycle1 => "0",
clken_out1 => "0",
bypass2 => "0",
outdiv2 => "000100",
en_phase2 => "1",
static_phase2 => "000",
dyn_phase2 => "0",
byp_clkdiv2 => "1",
high_cnt2 => "0000000000",
low_cnt2 => "0000000000",
half_cycle2 => "0",
clken_out2 => "0",
bypass3 => "0",
outdiv3 => "000100",
en_phase3 => "1",
static_phase3 => "000",