Achronix Speedster22i User Macro Guide - Manual (Page 207)

PLL/DLL Clock Generators ACX_CLKGEN
Speedster Macro Cell Library www.achronix.com PAGE 190
Parameters
Table 9-2: Parameters
Parameter Description Defined Values
Default
Value
clkdiv Reference Divider value. 6’h01 - 6’h24 6’h1
intfb Internal Feedback Enable.
0: Disable internal feedback.
1: Enables (internal) feedback divisor.
1’b0,1’b1
1’b0
phaseinc_sat Mixed Feedback Mode. Not supported if intfb=0.
0: Pure internal feedback mode (if intfb = 1),
Pure external feedback mode (if intfb = 0)
1: Mixed feedback mode (if intfb = 1).
1’b0,1’b1 1’b0
clkmult Feedback Divider Divisor Value. Integer mode:8’h02-8’h42,
Fractional mode: 8’h8-8’h42
8’h0
synthmode Feedback Divider Mode.
0: Integer mode.
1: Fractional mode. Uses frac_div_ctrl
1’b0,1’b1 1’b0
frac_div_ctrl Feedback Divider Fractional Portion. (requires synth-
mode = 1). In fractional mode, frac_div_ctrl is the 16-bit
numerator which is divided by 65536. The resultant
fraction is then used to scale the Feedback Divider
value.
16’h0000-16’hFFFF 16’h0000
rst_short_long Unused. 1’b0,1’b1 1’b0
clkouten_mode Clock Enable Mode.
0: Enable clock outputs with the clken_out0 -
clken_out3 parameters.
1: Enable clock outputs with the core_clken[3:0]
inputs.
1’b0,1’b1 1’b0
pll_user_reset_en PLL User Reset Enable.
0: Disable PLL rstn input.
1: Enable PLL rstn input.
1’b0,1’b1 1’b0
pll_user_outrst_en PLL User Output Phase Reset Enable.
0: Disable PLL outphrstn input.
1: Enable PLL outphrstn input.
1’b0,1’b1 1’b0
pll_user_csrrst_en PLL User Reset Enable for Serial Control Bus block.
0: Disable PLL ick_dspll_sif_rstn input.
1: Enable PLL ick_dspll_sif_rstn input.
1’b0,1’b1 1’b0
bypass0 Clkout[0] Bypass.
0: clkout[0] driven by PLL output.
1: clkout[0] driven by refclk input.
1’b0,1’b1 1’b0
bypass1 Clkout[1] Bypass.
0: clkout[1] driven by PLL output.
1: clkout[1] driven by refclk input.
1’b0,1’b1 1’b0