Table - table 2-9: function table, Heading3 - verilog instantiation template, Heading3 - vhdl instantiation template – Achronix Speedster22i User Macro Guide User Manual
Page 70
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Registers
DFFEC
Speedster22i Macro Cell Library
PAGE 54
Table 2-9: Function Table
Inputs
Output
cn
ce
d
ck
q
Verilog Instantiation Template
DFFEC #(.init(1’b0))
instance_name
(.q(user_out),
.d(user_din),
.cn(user_clear),
.ce(user_clock_enable),
.ck(user_clock));
VHDL Instantiation Template
------------- ACHRONIX LIBRARY ------------
library speedster22i;
use speedster22i.components.all;
------------- DONE ACHRONIX LIBRARY ---------
-- Component Instantiation
DFFEC_instance_name : DFFEC
generic map ( init => ‘0’)
port map (q => user_out,
d => user_din,
cn => user_clear,
ce => user_clock_enable,
ck => user_clock);
X
0
X
X
Hold
0
1
X
0
1
1
0
0
1
1
1
1
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