Achronix Speedster22i User Macro Guide - Manual (Page 46)

I/O Cells OPAD_D
Speedster Macro Cell Library www.achronix.com PAGE 29
OPAD_D
Registered Output Pad with Asynchronous or Synchronous Set/Reset
q
ce
d
rstn
rstn
din pad
clk
data_en
OPAD_D
Figure 1-15: OPAD_D Logic Symbol
OPAD_D is a registered output pad. The output register is clocked on the rising edge of the
clock. Driving rstn low performs an asynchronous initialization of the output register if the
rstmode parameter is set to async and performs a sychronous initialization of the output
register if the rstmode parameter is set to sync. The value initialized into the output register is
determined by the value of the rstvalue parameter.
Table 1-33: Ports
Name Type Description
pad Device output pad.
din
Positive-edge based data input. Data is clocked into the output register
upon the rising edge of the clk input, and is driven to the pad.
data_en
Output Register Clock Enable. A high value on data_en enables the Out-
put Register to clock the din input to the output at the next rising edge of
the clock. A low value on data_en allows the Output Register to retain its
current value.
rstn
Output Register Reset. If the value of the rstmode parameter is “async”, a
low value on the rstn input performs an asynchronous initialization of the
Output Register. If the value of the rstmode parameter is “sync”, a low value
on the rstn input performs a synchronous initialization of the Output Reg-
ister on the next rising edge of the clock. The value initialized into the Out-
put Register is determined by the value of the rstvalue parameter.
clk Output Register Clock input.
output
input
input
input
input