Kontron VMP3 - Manual (Page 69)

VMP3 Configuration
ID 29230, Rev. 01 © 2005 Kontron Modular Computers GmbH Page 4 - 9
29230
.01.UG.VC.050727/091435
P R E L I M I N A R Y
For information regarding the required hardware resources, refer to chapter “Interrupt
Mapping” in this manual. A logical ’1’ indicates that an interrupt has been asserted.
4.2.8 Watchdog Control Register
The Watchdog Control register is the interface between applications and the operating system
for controlling the functioning of the Watchdog timer. There are four possible modes of opera-
tion involving the Watchdog timer:
• Timer only
• Reset
• Interrupt
• Dual stage
At power on the Watchdog is not enabled. If not required, it is not necessary to enable it. If re-
quired, the bits of the Watchdog Control register must be set according to application require-
ments. To operate the Watchdog, the mode and time period required must first be set and then
the Watchdog enabled. Once enabled, the Watchdog can only be disabled or the mode
changed by powering down and then up again. To prevent a Watchdog timeout the Watchdog
must be retriggered before timing out. This is done by writing a ’1’ to the WTR bit. In the event
a Watchdog timeout does occur, the WTE bit is set to ’1’. What transpires after this depends on
the mode selected. The four operational Watchdog timer modes are described as follows.
Timer only - In this mode the Watchdog is enabled using the required timeout period. Normally
the Watchdog is retriggered by writing a ’1’ to the WTR bit. In the event a timeout occurs, the
WTE bit is set to ’1’. This bit can then be polled by the application and handled accordingly. To
continue using the Watchdog, write a ’1’ to the WTE bit, and then retrigger the Watchdog using
WTR. The WTE bit retains its setting as long as no power down-up is done. Therefore, this bit
may be used to verify the status of the Watchdog.
Reset mode - This mode is used to force a hard reset in the event of a Watchdog timeout. To
be effective, the hard reset must not be masked or otherwise negated. In addition, the WTE bit
is not reset by the hard reset which makes it available if necessary to determine the status of
the Watchdog prior to the reset.
Interrupt mode - This mode causes the generation of an interrupt in the event of a Watchdog
timeout. The interrupt handling is a function of the application. If required the WTE bit can be
used to determine if a Watchdog timeout has occurred.
Dual stage mode - This a complex mode where in the event of a timeout two things occur: 1)
an interrupt is generated, and 2) the Watchdog is retriggered automatically. In the event a
second timeout occurs immediately following the first timeout, a hard reset will be generated.
If the Watchdog is retriggered normally, operation continues. The interrupt generated at the first
timeout is available to the application to handle the first timeout if required. As with all of the
Table 4-8: Device Interrupt Pending Register
REGISTER NAME DEVICE INTERRUPT PENDING ACCESS
ADDRESS 0xFFFF A006 R
BIT POSITION
MSB
7 6 5 4 3 2 1 0
LSB
CONTENT res. TEMP FCC2 FCC1 SER4 SER3 SER2 SER1
DEFAULT 0 0 0 0 0 0 0 0