Cisco 15327 User Manual

Page 21

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Figures

xxi

Ethernet Card Software Feature and Configuration Guide, R7.2

Figure 21-3

Unwrapped Cisco proprietary RPR with Unidirectional Excessive CRC Errors

21-10

Figure 21-4

Wrapped Cisco proprietary RPR with Bidirectional Excessive CRC Errors

21-11

Figure 21-5

First Stage of Unwrapped Cisco proprietary RPR with Bidirectional Excessive CRC Errors

21-12

Figure 21-6

Second Stage of Unwrapped Cisco proprietary RPR with Bidirectional Excessive CRC Errors

21-13

Figure 22-1

SNMP on the ML-Series Card Example

22-2

Figure 22-2

SNMP Network

22-4

Figure 23-1

Data Traffic on a G-Series Point-to-Point Circuit

23-3

Figure 23-2

G-Series Gigabit EtherChannel (GEC) Support

23-5

Figure 23-3

End-to-End Ethernet Link Integrity Support

23-5

Figure 23-4

G-Series Point-to-Point Circuit

23-7

Figure 23-5

G-Series Manual Cross-Connects

23-8

Figure 23-6

Card Level Overview of G-Series One-Port Transponder Mode Application

23-9

Figure 23-7

G-Series in Default SONET/SDH Mode

23-9

Figure 23-8

G-Series Card in Transponder Mode (Two-Port Bidirectional)

23-10

Figure 23-9

One-Port Bidirectional Transponder Mode

23-11

Figure 23-10

Two-Port Unidirectional Transponder

23-12

Figure 23-11

Multicard EtherSwitch Configuration

23-14

Figure 23-12

Single-Card EtherSwitch Configuration

23-15

Figure 23-13

E-Series Mapping Ethernet Ports to STS/VC Circuits

23-15

Figure 23-14

Edit Circuit Dialog Box Featuring Available VLANs

23-18

Figure 23-15

Q-tag Moving Through VLAN

23-19

Figure 23-16

Priority Queuing Process

23-20

Figure 23-17

STP Blocked Path

23-21

Figure 23-18

Spanning Tree Map on Circuit Window

23-22

Figure 23-19

Multicard EtherSwitch Point-to-Point Circuit

23-24

Figure 23-20

Single-Card EtherSwitch or Port-Mapped Point-to-Point Circuit

23-25

Figure 23-21

Shared Packet Ring Ethernet Circuit

23-25

Figure 23-22

Hub-and-Spoke Ethernet Circuit

23-26

Figure 24-1

CE-100T-8 Point-to-Point Circuit

24-1

Figure 24-2

Flow Control

24-3

Figure 24-3

End-to-End Ethernet Link Integrity Support

24-3

Figure 24-4

CE-100T-8 Allocation Tab for SDH

24-12

Figure 24-5

CE-100T-8 STS/VT Allocation Tab

24-13

Figure 25-1

CE-1000-4 Point-to-Point Circuit

25-2

Figure 25-2

Flow Control

25-3

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