ADLINK PXIS-2719A - Manual (Page 25)

Introduction 15
PXIS-2719A
Table 1-5: Trigger Bus Settings
1.5.7 System Reference Clock
The PXIS-2719A supplies a PXI 10MHz system reference clock
(PXI_CLK10) to each peripheral slot for inter-module synchroniza-
tion. An independent buffer (having source impedance matched to
the backplane and a skew of less than 1 ns between slots) drives
the clock signal generated from a high-precision oscillator to each
peripheral slot.
This common reference clock signal can synchronize multiple
modules in a PXI chassis. The 10 MHz reference clock is impor-
tant to the PXI specification for inter-module synchronization. PXI
modules which have phase-locker loop circuit can lock the 10
MHz reference clock to generate an in-phase timebase.
The PXIS-2719A PXI chassis automatically selects the source of
the 10 MHz reference clock from
X
Built-in accurate 10 MHz oscillator
X
External 10 MHz clock through a BNC connector
X
PXI_CLK10_IN pin on the star trigger slot
P2 P3 P4 P5 Configuration Description
x x x x N/A N/A
OFF OFF x x All Segments
Isolated All Segments Isolated
ON ON ON ON 1 → 2 → 3 Segment 1 to 2 & 3
ON OFF ON OFF 1 → 2 Segment 1 to 2
ON OFF OFF OFF 1 ← 2 Segment 2 to 1
OFF ON OFF ON 2 → 3 Segment 2 to 3
OFF ON OFF OFF 2 ← 3 Segment 3 to 2
ON ON OFF OFF 1 ← 2 ← 3 Segment 3 to 1 & 2
ON ON OFF ON 1 ← 2 → 3 Segment 2 to 1 & 3