ADLINK PXIe-9852 - Manual (Page 15)

Introduction 5
PXIe-9852
Table 1-1: Timebase
1.3.3 Triggers
Table 1-2: Trigger Source & Mode
Table 1-3: Digital Trigger Input
External reference
clock
10MHz
External reference
clock input range
500mVpp ~ 5Vpp
AC / DC
compliant, 50Ω
load
impedance
External sampling
clock input range
1Vpp ~ 5Vpp
AC / DC
compliant, 50Ω
load
impedance
Trigger Source & Mode
Trigger source
Software, external digital trigger, analog trigger,
PXI_STAR, PXI_trigger bus [0..7], and PXIe_DSTARB
Trigger mode
Post trigger, delay trigger, pre-trigger, or middle trigger,
re-trigger for post trigger and delay trigger modes
Digital Trigger Input
Sources
Front panel SMA connector
Compatibility 3.3 V TTL, 5 V tolerant
Input high threshold 2.0 V
Input low threshold (VIL) 0.8 V
Maximum input overload -0.5 V ~ +5.5 V
Trigger polarity
Rising or falling edge
Pulse width 20 ns minimum
Sample Clock Comment