ADLINK PXIe-9852 - Manual (Page 39)

Operations 29
PXIe-9852
Table 3-4: Counter Parameters and Description
3.7 Synchronizing Multiple Modules
The SSI (System Synchronization Interface) of the PXIe-9852 is
achieved by a trigger signal, pre_data_ready signal(s) and a refer-
ence clock, all transmitted through PXI_BUS ports to enable multi-
ple module synchronization. When synchronizing multiple devices,
a PXIe-9852 can be configured as a master or a slave, wherein
the system accommodates multiple slave devices but only a single
master device. For better synchronization between multiple
devices, all connected PXIe-9852s should refer to the same time
base. The time base can be PXI_CLK 10, PXIe_CLK 100, or an
external clock through the front panel.
When operating in post-trig or delay-trig mode, the only trigger sig-
nal transmitted through PXI BUS is SSI_TRIG1, used to initiate
acquisition of all devices. A master device should set one
PXI_BUS pin in output direction. The trigger signal will be sent out
through this pin to other slave devices on PXI_BUS. All slave
devices should set the trigger signal from the corresponding
PXI_BUS pin so that all devices on PXI_BUS are triggered simul-
taneously.
When any device on PXI_BUS is required to operate in pre-trig or
mid-trig mode, the master device must be set correspondingly.
The trigger modes of other slave devices are not limited. A slave
device in pre-trig/mid-trig mode transmits a pre_data_ready signal
to inform the master device that it is ready to accept trigger signals
(for more details of pre-trig and mid-trig status, please see “Pre-
ReTrgCnt 31-bit 1-2147483647 Enables re-trigger to accept
multiple triggers.
X 1 - 2147483647 for
normal operation
X 1 - 65535 for Data
Average mode
See Acquisition with Re-
Triggering
Counter
Name
Length Valid Value Description