ADLINK PXIe-9852 - Manual (Page 28)

18 Operations
Figure 3-2: Linked List of PCI Address DMA Descriptors
3.3 Trigger Source and Trigger Modes
This section details PXIe-9852 triggering operations.
Figure 3-3: Trigger Architecture of the PXIe-9852
The PXIe-9852 requires a trigger to implement acquisition of data.
Configuration of triggers requires identification of trigger
First PXI Address
First Dual Address
Transfer Size
Next Descriptor
PXI Address
Dual Address
Transfer Size
Next Descriptor
PXI Address
Dual Address
Transfer Size
Next Descriptor
PXI Express Bus
Local Memory
(FIFO)
Trigg
er sou
rce MUX
Digital Trigger In
Software trigger
Trigger
Decision
To Internal FPGA Circuits
Trigge
r Outpu
t MUX
PX
I T
rig
g
e
r Bu
s
Analog trigger ch0
Analog trigger ch1
PX
I Trig
ger B
u
s PXI_STAR
PXIe_DSTARB
PXI_TriggerBus[0:7]
SSI_TRIG1
TRG OUT
TRG IN