ADLINK PXIe-9852 - Manual (Page 7)

List of Figures vii
PXIe-9852
List of Figures
Figure 1-1: Analog Input Channel Bandwidth, ±0.2 Vpp............... 3
Figure 1-2: Analog Input Channel Bandwidth, ±2 Vpp.................. 4
Figure 1-3: PXIe-9852 Schematic................................................. 8
Figure 1-4: PXIe-9852 I/O Array ................................................... 9
Figure 3-1: Analog Input Architecture of the PXIe-9852 ............. 15
Figure 3-2: Linked List of PCI Address DMA Descriptors ........... 18
Figure 3-3: Trigger Architecture of the PXIe-9852 ...................... 18
Figure 3-4: External Digital Trigger ............................................. 19
Figure 3-5: Post-Trigger Acquisition ........................................... 21
Figure 3-6: Delayed Trigger Mode Acquisition............................ 22
Figure 3-7: Pre-Trigger Mode Acquisition ................................... 22
Figure 3-8: Middle Trigger Mode Acquisition .............................. 23
Figure 3-9: Re-Trigger Mode Acquisition .................................... 24
Figure 3-10: PXIe-9852 Clock Architecture .................................. 25
Figure 3-11: PXIe-9852 Timebase Architecture............................ 26
Figure 3-12: Basic Digitizer Acquisition Timing............................. 27
Figure 3-13: Varying Sampling Rates by Adjusting Scan Interval
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