ADLINK PXIe-9529 - Manual (Page 34)

24 Operations
3.5.2 DDS Timing vs. ADC
Table 3-5: Timing Relationship between ADC and PLL Clock
3.5.3 Filter Delay in ADC
Filter delay indicates time required for data propagation through a
converter. Both AI channels experience filter delay due to filter
circuitry and converter architecture, as shown.
Table 3-6: ADC Filter Delay
3.6 Synchronizing Multiple Modules
The SSI (System Synchronization Interface) provides DAQ timing
synchronization between multiple cards, with a bidirectional SSI
I/O providing flexible connection between cards and allowing a
single SSI master to output the signal to other slave modules. SSI
signals are designed for card synchronization only, not external
devices. In the PXI Express form factor, the PXI trigger bus built
on the PXI Express backplane provides the necessary timing sig-
nal connections. All SSI signals are routed to the XJ4 connector,
with no requirement for additional cabling. The eight intercon-
nected lines on the PXI Express backplane, labeled PXI Trigger
Bus[0:7] provide a flexible interface for syncing multiple modules.
The PXIe-9529 utilizes the PXI Trigger Bus [0:7] as a System Syn-
chronization Interface (SSI). Flexible routing of timebase clock and
trigger signals onto the PXI Trigger Bus enables the PXIe-9529 to
simplify synchronization between multiple modules.The bidirec-
tional SSI I/O provides flexible connection between modules,
Sampling Rate 8k – 54kS/s 54k - 108kS/s 108 k – 192kS/s
DDS(PLL) CLK
6.144
M-41.472
MHz
13.824
M-27.648 MHz 20.736
M-36.864 MHz
Update Rate (kS/s) Filter Delay (samples)
8 K - 54 kS/s 13
54 K - 108 kS/s 13
108 K-192 kS/s 5