ADLINK PXIe-9529 - Manual (Page 7)

List of Figures vii
PXIe-9529
List of Figures
Figure 1-1: Analog Input Channel Bandwidth, ±0.2 Vpp............... 4
Figure 1-2: Analog Input Channel Bandwidth, ±2 Vpp.................. 5
Figure 1-3: PXIe-9529 Schematic................................................. 8
Figure 1-4: PXIe-9529 I/O Array ................................................... 9
Figure 3-1: Analog Input Architecture ......................................... 13
Figure 3-2: Linked List of PCI Address DMA Descriptors ........... 17
Figure 3-3: Trigger Architecture .................................................. 18
Figure 3-4: External Digital Trigger ............................................. 19
Figure 3-5: Analog Trigger Conditions ........................................ 20
Figure 3-6: Post-Trigger Acquisition ........................................... 22
Figure 3-7: Delay Trigger Mode Acquisition................................ 22
Figure 3-8: Re-Trigger Mode Acquisition .................................... 23
Figure 3-9: Timebase Architecture.............................................. 23
Figure 3-10: SSI Architecture........................................................ 25