ADLINK PXIe-9529 - Manual (Page 35)

Operations 25
PXIe-9529
allowing the single SSI master PXIe-9529 to output the SSI sig-
nals to other slave modules. SSI timing signals and functions are
as shown, as is the SSI architecture.
Table 3-7: SSI Timing Signal Definitions
Figure 3-10: SSI Architecture
SSI Timing Signal Functionality
SSI_TIMEBASE
SSI master: issues TIMEBASE
SSI slave: accepts SSI_TIMEBASE to replace
the internal TIMEBASE signal.
SSI_SYNC_START
SSI master: issues internal SYNC_START
SSI slave: accepts SSI_SYNC_START as the
digital trigger signal.
SSI_AD_TRIG
SSI master: issues internal AD_TRIG
SSI slave: accepts SSI_AD_TRIG as the digital
trigger signal.
SSI_AD_TRG
SSI_SYNC_START
SSI_TIMEBASE
PXI Interface
PXI Trigger
Bus[0:7]
Timing Control
One
Trigger Bus
[7..0]
One
Trigger Bus
[7..0]
One
Trigger Bus
[7..0]
SSI_AD_TRIG
SSI_SYNC_ST
ART