ADLINK cBP-3062 - Manual (Page 33)

Power Supply Unit
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input for DC input power supplies. Front panel keying is provided to
prevent damaging an AC power supply inserted into a backplane
wired for DC and vice versa.
CGND Chassis GND signal shall be connected to safety ground with a low
impedance connection.
V1ADJ V1 output voltage may be margined up to +10% if V1ADJ input is
pulled to RTN or -10% if pulled to V1 using a programming resistor
network. Typically usage is Rt=10K . See Figure 2.1. An open
circuit on the backplane shall result in a nominal output voltage.
V2ADJ V2 output voltage may be margined up to +10% if V2ADJ input is
pulled to RTN or -10% if pulled to V2 using a programming resistor
network. Typically usage is Rt=10K . See Figure 2.1. An open
circuit on the backplane shall result in a nominal output voltage.
DEG# Derating signal MAY be used as an output from the power supply to
indicate that the supply is beginning to derate its power output. This
signal is active low. It is a open collector, and should be pulled high
by a 10K resistor. Note that backplanes providing a power supply
connector shall connect DEG# to the backplane signal DEG# in the
event that a power supply implementing this signal is installed.
FAL# Supply Fail signal MAY be used as an output from the power supply
to indicate that it has failed. This signal is active low. It is a open
collector, and should be pulled high by a 10K resistor. Note that
backplanes providing a power supply connector shall connect FAL#
to the backplane signal FAL# in the event that a power supply
implementing this signal is installed.
GA[2..0] The physical slot address (GA[2..0]) shall be encoded on the
backplane by grounding and leaving unconnected different
combinations of pins at each connector. Physical slot addresses are
defined by the physical slot number on the platform per Table 3-2-1.
Due to the limited number of power supply geographic addresses
available, physical slot numbers for power supplies are independent
of physical slot numbers for CompactPCI boards. Power supply
physical slot numbers shall start at 0 in the top-left corner of the card
cage. Each signal shall be pulled up with a 10.KO ± 10% resistor on
any power supply using the geographic addressing signals GA[2..0].
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Caution:
1. Improperly connected 5S+,5S-, 3S+, and 3S- leads may damage the
power supply.
2. Because implementation and timing for V1 SHARE, V2 SHARE may
vary from manufacturer to manufacturer, interoperability between two or
more power supplies from different manufacturers is not guaranteed.