ADLINK CoreModule 430 - Manual (Page 34)

Chapter 3 Hardware
28 Reference Manual CoreModule 430
Serial Peripheral Interface (SPI)
The CoreModule 430 provides an SPI header for programming the SPI Flash virtual floppy drive.
Table 3-13 describes the pin signals of the SPI header, which provides a single-row of 6 pins with 0.079"
(2mm) pitch.
Note: The shaded table cells denote power or ground. The * symbol indicates the signal is Active Low.
Low Pin Count Interface (LPC)
The LPC interface provides expansion for custom LPC devices.
Table 3-14 describes the pin signals of the LPC interface, which uses a 10-pin header with 2 rows, odd/even
sequence (1, 2), and 0.079" (2mm) pitch.
Note: The shaded table cells denotes power or ground.
Miscellaneous
Real Time Clock (RTC)
The CoreModule 430 contains a Real Time (time of day) Clock (RTC), which can be backed up with an
external cell battery. The CoreModule 430 will function without a battery in those environments which
prohibit batteries. The CoreModule 430 will also continue to operate after the battery life has been
exceeded. Under these conditions all setup information is restored from the on-board Flash memory during
POST along with the default date and time information.
Table 3-13. SPI Interface Pin/Signal Descriptions (J19)
Pin # Signal Description
1 EXT_CS* SPI Chip Select
2 EXT_CLK SPI Clock
3 EXT_DO SPI Data Out
4 EXT_DI SPI Data In
5 V.3.3 +3.3 Volts Power
6 GND Ground
Table 3-14. LPC Interface Pin/Signal Descriptions (J20)
Pin # Signal Description
1 AD0 Command, Address, and Data 0
2 SERIRQ Serial Interrupt Request
3 AD1 Command, Address, and Data 1
4 DRQ DMA Request
5 AD2 Command, Address, and Data 2
6 FRAME Frame Signals - indicate start of new cycle or termination of broken cycle
7 AD3 Command, Address, and Data 3
8 CLK_PCI PCI Clock
9 V.3.3 +3.3 Volts Power
10 GND Ground
NOTE Some operating systems require a valid default date and time to function.