Altera MAX 10 FPGA - Manual (Page 40)

Figure 3-2: Error Detection Block Diagram with Interfaces for MAX 10 Devices
Clock Divider
(1 to 256 Factor)
Pre-Computed CRC
(Saved in the Option Register)
CRC
Computation
Error Detection
Logic
SRAM
Bits
CRC_ERROR
(Shown in BIDIR Mode)
VCC
Logic Array
CLK
SHIFTNLD
LDSRC
REGOUT
CRC_ERROR
Internal Chip Oscillator
The following example shows how the input and output ports of a WYSIWYG atom are defined in the
MAX 10 device.
fiftyfivenm_crcblock <name>
(
.clk(<ED_CLK clock source>),
.shiftnld(<ED_SHIFTNLD source>),
.ldsrc (<LDSRC source>),
.crcerror(<CRCERROR_CORE out destination>),
.regout(<output destination>)
);
defparam <crcblock_name>.oscillator_divider = <internal oscillator division (1 to
256)>;
Related Information
• SEU Mitigation and Configuration Error Detection on page 2-18
• Error Detection Timing on page 2-20
Enabling Data Compression
When you enable compression, the Quartus II software generates configuration files with compressed
configuration data.
A compressed configuration file is needed to use the dual configuration mode in the internal configura‐
tion scheme. This compressed file reduces the storage requirements in internal flash memory, and
decreases the time needed to send the bitstream to the MAX 10 device family. There are two methods to
enable compression for the MAX 10 device family bitstreams in the Quartus II software:
3-10 Enabling Data Compression
UG-M10CONFIG
2015.05.04
Altera Corporation MAX 10 FPGA Configuration Design Guidelines
Send Feedback