Altera FIR Compiler II MegaCore Function - Manual (Page 31)

MSB and LSB Truncation, Saturation, and Rounding
The output options on the parameter editor allow you to truncate or saturate the MSB and to truncate or
round the LSB. Saturation, truncation, and rounding are non-linear operations.
Table 3-4: Options for Limiting Precision
Bit
Range
Option Result
MSB
Truncat
e
In truncation, the filter disregards specified bits..
Saturate In saturation, if the filtered output is greater than the
maximum positive or negative value that can be
represented, the output is forced (or saturated) to the
maximum positive or negative value.
LSB
Truncat
e
Same process as for MSB.
Round The output is rounded away from zero.
Figure 3-1: Removing Bits from the MSB and LSB
D15
D14
D13
D12
D11
D10
D9
D8
.
.
D0
D9
D8
.
.
D0
Bits Removed from MSB
Full
Precision
Limited
Precision
D15
D14
.
.
.
.
D4
D3
D2
D1
D0 D11
D10
.
.
.
D1
D0
Bits Removed from LSB
Full
Precision
Limited
Precision
D15
D14
D13
D12
.
.
.
D3
D2
D1
D0
D10
D9
.
.
.
D1
D0
Bits Removed from both MSB & LSB
Full
Precision
Limited
Precision
Memory and Multiplier Trade-Offs
When the Quartus II software synthesizes your design to logic, it often creates delay blocks. The FIR II IP
core tries to balance the implementation between logic elements (LEs) and memory blocks (M512, M4K,
M9K, or M144K). The exact trade-off depends on the target FPGA family, but generally the trade-off
attempts to minimize the absolute silicon area used. For example, if a block of RAM occupies the silicon
area of two logic array blocks (LABs), a delay requiring more than 20 LEs (two LABs) is implemented as a
block of RAM. However, you want to influence this trade-off.
Table 3-5: Implementation Options
Parameter Value Description
Resource Optimization Settings
3-6 MSB and LSB Truncation, Saturation, and Rounding
UG-01072
2014.12.15
Altera Corporation FIR II IP Core Parameters
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