Altera FIR Compiler II MegaCore Function - Manual (Page 49)

Figure 4-17: Four Channels on Four Wires (Output)
clk
xOut_v
xOut_0
xOut_1
xOut_2 C0
C1
C2
xOut_3 C3
This result appears to be vertical, but that is because the number of cycles is 1, so on each wire there is
only space for one piece of data.
Figure 4-18: Four Channels on Four Wires with Double Clock Rate (Input)
clk
xln_v
xln_0
xln_1 C0 C1
C2 C3
Figure 4-19: Four Channels on Four Wires with Double Clock Rate (Output)
clk
xOut_v
xOut_0
xOut_1 C0 C1
C2 C3
15 Channels with 15 Valid Cycles and 17 Invalid Cycles
Sometimes invalid cycles are inserted between the input data. An example where the clock rate = 320,
sample rate = 10, yields a TDM factor of 32, inputChannelNum = 15, and interpolation factor is 10. In this
case, the TDM factor is greater than inputChannelNum. The optimization produces a filter with
PhysChanIn = 1, ChansPerPhyIn = 15, PhysChanOut = 5, and ChansPerPhyOut = 3.
The input data format in this case is 32 cycles long, which comes from the TDM factor. The number of
channels is 15, so the filter expects 15 valid cycles together in a block, followed by 17 invalid cycles. You
can insert extra invalid cycles at the end, but they must not interrupt the packets of data after the process
has started. If the input sample rate is less than the clock rate, the pattern is always the same: a repeating
cycle, as long as the TDM factor, with the number of channels as the number of valid cycles required, and
the remainder as invalid cycles.
4-16 15 Channels with 15 Valid Cycles and 17 Invalid Cycles
UG-01072
2014.12.15
Altera Corporation FIR II IP Core Functional Description
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