Altera FIR Compiler II MegaCore Function User Manual
Page 47
Figure 4-10: Channelization for Four Channels with a TDM Factor of 3
A TDM factor of 3 combines four input channels into two wires (inputChannelNum = 4,
ChanWireCount = 2, ChanCycleCount = 2). This example shows two wires to carry the four channels and
the cycle count is two on each wire. The channels are evenly distributed on each wire leaving the third
time slot as don't care on each wire.
clock
input_valid
input_data_channel_0
input_data_channel_1
input_data_channel_2
input_data_channel_3
input_channel
output_valid
output_data_wire_1
output_data_wire_2
output_channel
c0(0)
c0(1)
c0(2)
c1(0)
c1(1)
c1(2)
c2(0)
c2(1)
c2(2)
c3(0)
c3(1)
c3(2)
c0(0)
c0(1)
c0(2)
c1(0)
c1(1)
c1(2)
c2(0)
c2(1)
c2(2)
c3(0)
c3(1)
c3(2)
don’t care
don’t care
don’t care
don’t care
The channel signal is used for synchronization and scheduling of data. It specifies the channel data
separation per wire. Note that the channel signal counts from 0 to ChanCycleCount–1 in synchronization
with the data. Thus, for ChanCycleCount = 1, the channel signal is the same as the channel count,
enumerated from 0 to inputChannelNum–1.
For a case with single wire, the channel signal is the same as a channel count.
Figure 4-11: Four Channels on One Wire with No Invalid Cycles
valid
channel
data0
0
1
2
3
0
1
2
3
c0(0)
c1(0)
c2(0)
c3(0)
c0(1)
c1(1)
c2(1)
c3(1)
For ChanWireCount > 1, the channel signal specifies the channel data separation per wire, rather than the
actual channel number. The channel signal counts from 0 to ChanCycleCount–1 rather than 0 to
inputChannelNum–1.
Figure 4-12: Four Channels on Two Wires with No Invalid Cycles
valid
channel
data0
data1
0
1
0
1
0
1
0
1
c0(0)
c1(0)
c0(1)
c1(1)
c0(2)
c1(2)
c0(3)
c1(3)
c2(0)
c3(0)
c2(1)
c3(1)
c2(2)
c3(2)
c2(3)
c2(3)
Notice that the channel signal remains a single wire, not a wire for each data wire. It counts from 0 to
ChanCycleCount–1.
4-14
Channelization
UG-01072
2014.12.15
Altera Corporation
FIR II IP Core Functional Description