Altera FIR Compiler II MegaCore Function - Manual (Page 37)

Multiple Channels on Single Wire
Figure 4-3: Multiple Channels on Single Wire Sink to FIR II IP core
When transferring a packet of data over multiple channels on a single wire. The data width of each
channel is 8 bits
FIR Filter
xln_v
xln_0[7:0]
ast_sink_valid
ast_sink_data[7:0]
Controller
ast_sink_ready
FIR Compiler II MegaCore Function
Sink
sink_ready
control signals
ast_sink_eop
ast_sink_sop
ast_sink_error
packet error
Avalon
Streaming
Interface
Signals Check
Multiple Channels on Multiple Wires
In this example, hardware optimization produces a TDM factor of 2, number of channel wires = 3, and
channels per wire = 2.
4-4 Multiple Channels on Single Wire
UG-01072
2014.12.15
Altera Corporation FIR II IP Core Functional Description
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