Altera RapidIO II MegaCore Function - Manual (Page 116)

4–74 Chapter 4: Functional Description
Physical Layer
RapidIO II MegaCore Function August 2014 Altera Corporation
User Guide
■ FIFO buffer with level output port
■ Four transmission queues and four retransmission queues to handle packet
prioritization
Physical Layer Interfaces
Figure 4–28 shows the interfaces that the Physical layer supports.
Low-level Interface Receiver
The receiver in the low-level interface receives the input from the RapidIO interface,
and performs the following tasks:
■ Separates packets and control symbols
■ Removes IDLE2 idle sequence characters
■ Detects multicast-event and stomp control symbols
■ Detects packet-size errors
■ Checks the control symbol 13-bit CRC and asserts symbol_error if the CRC is
incorrect
Receiver Transceiver
The receiver transceiver is an embedded Altera Transceiver Native PHY IP core.
f For information about the Altera Transceiver Native PHY IP core, refer to the Altera
Transceiver PHY IP Core User Guide .
Figure 4–28. Physical Layer High Level Block Diagram
td rd tx_pll_refclk
sys_clk
Status Packet
and
Error Monitoring
Signals
Register-related
signals
rst_n
RapidIO Interface RapidIO Interface Transceiver
Signals
Low Latency
Signals
rx_clkout
Transport Layer
Registers
Low Level Interface
Transmitter
Transceiver
Transmitter
Receiver
Transceiver
Receiver
tx_clkout