Altera DSP Development Kit, Stratix V Edition - Manual (Page 42)

2–34 Chapter 2: Board Components
Components and Interfaces
DSP Development Kit, Stratix V Edition July 2012 Altera Corporation
Reference Manual
10/100/1000 Ethernet
The development board supports a 10/100/1000 BASE-T Ethernet connection using a
Marvell 88E1111 PHY device and the Altera Triple-Speed Ethernet MegaCore MAC
function. The device is an auto-negotiating Ethernet PHY with an SGMII interface to
the FPGA. The Stratix V GS device can communicate with the LVDS interfaces at up to
1.25 Gbps. The MAC function must be provided in the FPGA for typical networking
applications. The Marvell 88E1111 PHY uses 2.5-V and 1.0-V power rails and requires
a 25-MHz reference clock driven from a dedicated oscillator. It interfaces to an RJ-45
with internal magnetics that can be used for driving copper lines with Ethernet traffic.
Figure 2–7 shows the SGMII interface between the FPGA (MAC) and Marvell 88E1111
PHY.
Table 2–38 lists the Ethernet PHY interface pin assignments.
Figure 2–7. SGMII Interface between FPGA (MAC) and Marvell 88E1111 PHY
MAC
88E1111
Device
Transformer RJ45
SGMII Interface
S_IN ±
S_OUT ±
CAT 5 UTP:
- 10BASE-T
- 100BASE-TX
- 1000BASE-T
Table 2–38. Ethernet PHY Pin Assignments, Signal Names and Functions
Board
Reference
(U19)
Schematic Signal Name I/O Standard
Stratix V GS Device Pin
Number
Description
82 ENET_TX_P LVDS AB27 SGMII transmit
81 ENET_TX_N LVDS AC27 SGMII transmit
77 ENET_RX_P LVDS AP34 SGMII receive
75 ENET_RX_N LVDS AR34 SGMII receive
28 ENET_RESETn 2.5-V AA28 Device reset
25 ENET_MDC 2.5-V AA26 Management bus data clock
24 ENET_MDIO 2.5-V AA27 Management bus data
23 ENET_INTn 2.5-V AA29 Management bus Interrupt
74 ENET_LED_LINK100 2.5-V — 100-Mb link LED
73 ENET_LED_LINK1000 2.5-V — 1000-Mb link LED
69 ENET_LED_RX 2.5-V — RX data active LED
68 ENET_LED_TX 2.5-V — TX data active LED