Altera DSP Development Kit, Stratix V Edition - Manual (Page 6)

1–2 Chapter 1: Overview
Board Component Blocks
DSP Development Kit, Stratix V Edition July 2012 Altera Corporation
Reference Manual
Board Component Blocks
The board features the following major component blocks:
■ Altera Stratix V FPGA (5SGSMD5K2F40C2N) in the 1517-pin FineLine BGA
package
■ 457,000 LEs
■ 172,600 adaptive logic modules (ALMs)
■ 39-Mbits embedded memory
■ 36 transceivers (14.1 Gbps)
■ 174 full-duplex LVDS channels
■ 24 phase locked loops (PLLs)
■ 3,180 18x18-bit multipliers
■ 900-mV core voltage
■ 864 user I/Os
■ 1 PCI Express hard IP blocks
■ MAX ® V CPLD (5M2210ZF256C4) System Controller in the 256-pin FineLine BGA
package
■ 2,210 LEs
■ 203 user I/Os
■ 1.8-V core voltage
■ FPGA configuration circuitry
■ MAX II CPLD (EPM570GM100) and Flash Fast Passive Parallel (FPP)
configuration
■ On-Board USB-Blaster TM II for use with the Quartus ® II Programmer, Nios ® II
Software Build Tools, and System Console.
■ On-Board clocking circuitry
■ 50-MHz, 100-MHz, 125-MHz, and programmable oscillators
■ SMA connector for clock input (LVPECL)
■ Memory devices
■ 1152-Mbyte DDR3 SDRAM with a 72-bit data bus
■ 72-Mbyte CIO RLDRAM II with a 18-bit data bus
■ 4.5-Mbyte QDRII+ SRAM with a 18-bit data bus (footprint is compatible for
9-Mbyte QDRII with a 18-bit data bus)
■ Two 512-Mbyte synchronous flash with a 16-bit data bus