Altera DSP Development Kit, Stratix V Edition - Manual (Page 43)

Chapter 2: Board Components 2–35
Components and Interfaces
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Reference Manual
Table 2–39 lists the Ethernet PHY interface component reference and manufacturing
information.
High-Speed Mezzanine Cards (HSMC)
The development board contains two HSMC interfaces—port A and port B—to
provide 8 channels in port A and 4 channels in port B of 10.0 Gbps-capable
transceivers. Port A supports a full SPI4.2 interface (17 LVDS channels) and 3 input
and output clocks as well as SMBus and JTAG signals. The LVDS channels can be
used for CMOS signaling as well as LVDS. For Port B, other than the 3 input and
output clocks as well as SMBus and JTAG signals, it also covers the new DQS
standard to support daughtercards with external memory devices. For memory
support, the VCCIO banks for the HSMC port B is adjustable between 1.2 V, 1.5 V,
1.8 V, and 2.5 V. When the DQS features are not used, these channels can be used for
CMOS signaling.
The HSMC port A interface supports both single-ended and differential signaling.
The HSMC is an Altera-developed open specification, which allows you to expand
the functionality of the development board through the addition of daughtercards.
The HSMC port B is a new DQS standard to support both single-ended signaling and
external memory interfaces.
f
For more information about the HSMC specification such as signaling standards,
signal integrity, compatible connectors, cabling solutions, and mechanical
information, refer to the
High Speed Mezzanine Card (HSMC) Specification manual.
The HSMC connector has a total of 172 pins, including 120 signal pins, 39 power pins,
and 13 ground pins. The ground pins are located between the two rows of signal and
power pins, acting both as a shield and a reference. The HSMC host connector is
based on the 0.5 mm-pitch QSH/QTH family of high-speed, board-to-board
connectors from Samtec. There are three banks in this connector. Bank 1 has every
third pin removed as done in the QSH-DP/QTH-DP series. Bank 2 and bank 3 have
all the pins populated as done in the QSH/QTH series.
Table 2–39. Ethernet PHY Component Reference and Manufacturing Information
Board Reference Description Manufacturer
Manufacturing
Part Number
Manufacturer
Website
U19 Ethernet PHY BASE-T device
Marvel
Semiconductor
88E1111-B2-CAAIC000 www.marvell.com