Zilog Z16C30 User Manual
Page 104
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5-37
Z16C30 USC
®
U
SER
'
S
M
ANUAL
Z
ILOG
UM97USC0100
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
Reserved(0)
Wait4
Rx
Trig
RxStatBlk
Async:TxShaveL
Sync:TxPreL
Sync:TxPrePat
Flag
Pre
Amble
Wait4
Tx
Trig
TxCtrlBlk
Figure 5-16. The Channel Control Register (CCR)
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
RCCF
Ovflo
RCCF
Avail
Clear
RCCF
DPLL
Sync
DPLL
2Miss
DPLL
1Miss
DPLLEDGE
On
Loop
Loop
Send
Resrvd
TxResidue
/TxACK /RxACK
Figure 5-15. The Channel Command/Status Register (CCSR)
Last 1 or 2 character(s)
of frame or message "N"
Control Word for
frame or message "N+1"
Length of frame
or message "N+1"
First character(s) of
frame or message "N+1"
Address x
x+2
x+4
Address x+6
D15
D0
TxSubMode
TxResidue
0000000
00
D15
D12
D4
D2
Figure 5-17. A 32-bit Transmit Control Block in a DMA Buffer
UM009402-0201
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