Zilog Z16C30 - Manual (Page 138)

7-10
Z16C30 USC ®
U SER ' S M ANUAL
UM97USC0100
Z ILOG
7.9 INTERRUPT ACKNOWLEDGE CYCLES (Continued)
AD15-AD0
(not used) vector
/SITACK
/AS
IEO
IEI
/DS OR /RD
/WAIT//RDY
(as Wait)
/WAIT//RDY
(as Ack)
/INT
Figure 7-5. An Interrupt Acknowledge Cycle signalled by /SITACK, on a Multiplexed Bus
UM009402-0201