Zilog Z16C30 - Manual (Page 52)

4-3
Z16C30 USC ®
U SER ' S M ANUAL Z ILOG
UM97USC0100
CMCR13-12
CTR0
0 1 2 3
MUX
Q4 Q3 Q2 Q1 Q0
0 1 2 3
MUX
HCR15-14
RxC TxC
CMCR15-14
CTR0
0 1 2 3
MUX
Q4 Q3 Q2 Q1 Q0
0 1 2 3
MUX
0 1
MUX
HRC13
D REFCLK
RA
TE
MODE
DPLL
Rx Tx
HCR1
1-10
HCR9-8
CMCR7-6
0 1 2 3
MUX
BRG1 BRG0
CMCR9-8
0 1 2 3
MUX
CMCR1
1-10
0 1 2 3
MUX
LD DN
MODE
D
BRG0
Z
HALF
HCR1-0
TC0R
R S
LD DN
MODE
D
BRG1
Z
HALF
HCR5-4
TC1R
R S
CTR0/P0 CTR1/P1
MUX
0 1 2 3 4 5 6 7 CMCR2-0
MUX
0 1 2 3 4 5 6 7 CMCR5-3
MUX
0 1 2 3 4 5 6 7 IOCR2-0
MUX
0 1 2 3 4 5 6 7 IOCR5-3
DPLL
Rx
RxCHAR
TxCMPL
T
RxSYNC
TxCHAR
DPLL
Tx
CTR1/P1
RxCLK TxCLK
TxC RxC
RxD
CTR0/P0
Figure 4-1. A Model of a USC Channel’s Clocking Logic
UM009402-0201