Zilog Z16C30 - Manual (Page 205)

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Z16C30 USC ®
U SER ' S M ANUAL Z
ILOG
UM97USC0100
Q: Are there some rules of thumb to tune the device for
performance problems?
A: If you are experiencing RCC FIFO overflows, try in-
creasing the Rx DMA Trigger Level. This has the effect
of diminishing the overhead of DMA transfers on the
bus, which may give more bandwidth to the processor
for handling the End Of Frame condition. A less desir-
able alternative is to increase the number of bytes per
frame, which reduces the bandwidth required for
handling the End Of Frame condition.
If you are experiencing Rx FIFO overruns with inter-
rupts, either decrease the Rx FIFO Interrupt Level if the
overflow is occurring as a result of long interrupt
latency, or increase the Rx FIFO Interrupt Level if the
overflow is occurring as a result of processing during
the interrupt service routine. If the overruns are occur-
ring with DMA operation, decrease the Rx DMA Trig-
ger Level to better account for bus latency.
If you are experiencing Tx FIFO underruns with inter-
rupts, either decrease the Tx FIFO Interrupt Level if the
underrun is occurring as a result of long interrupt
latency, or increase the Tx FIFO Interrupt Level if the
underrun is occurring as a result of processing during
the interrupt service routine. If the underruns are
occurring with DMA operation, decrease the Tx DMA
Trigger Level to better account for bus latency.
Remember that when talking about levels in the FIFO,
the CPU sees the Rx side as the number of slots filled
and the Tx side as the number of slots available.
Q: While using the IUSC, the transmitter sends all data
correctly. The Rx DMA will receive bad data on every
other byte. Also the /RxREQ signal will change states
on every other byte. What is this a symptom of?
A: When using 16-bit DMA transfers, the DMA request
level values in the RICR must always be programmed
to at least 1, indicating 2 bytes received in the RxFIFO.
Similarly, the TICR must always be programmed to at
least 1, indicating 2 empty bytes in the TxFIFO. Other-
wise the serial channel will request what the DMA
thinks is a word transfer for every byte.
After programming the DMA request threshold, it is
good programming practice to write the TCSR or
RCSR to select the FIFO Fill Level, to prevent software
from inadvertently modifying the Interrupt or Request
Levels in the TICR or RICR.
Q: Does the Master Bus Request Enable bit (MBRE) in the
DCAR need to be “1” when doing register pointer
writes to the DCAR (for non-multiplexed slave ac-
cesses)?
A: When using indirect register addressing, software
typically should include a “1” in the MBRE bit when
writing a register address to the DCAR. If MBRE is
cleared when writing a register address to the DCAR,
the DMA channels are thereafter prevented from re-
questing and using the bus to transfer data to or from
the serial channel.
Q: Is it possible to use the Receive status block in basic
asynchronous mode? The customer wants to put each
received character by DMA in memory associated
with a status word.
A: No, both receive status blocks and transmit control
blocks only apply to “framed” protocols like HDLC.
Storing a status word with each byte can be done by
reading the RCSR before each data byte. Just read the
status before the data. This would have to be done
under interrupt control as a DMA would only pick up
the data.
Q: Is it possible to simultaneously use interrupts and DMA
to receive characters?
A: Yes, because the DMA and interrupt request thresh-
olds are programmed independently. Therefore, you
could interrupt on a fill level of 2 bytes, but DMA
request on 16. Such a scheme is fraught with perils, as
it may happen that the CPU and DMA could inadvert-
ently interleave FIFO reads. A better use of the DMA
request would be for some higher priority interrupt
since the normal interrupt had not yet been serviced.
UM009402-0201