Zilog Z16C30 - Manual (Page 41)

2-15
Z16C30 USC ®
U SER ' S M ANUAL Z ILOG
UM97USC0100
ADnn
Address Data
A//B, D//C
/CS
/SITACK
/PITACK,/WR,(/RD OR /DS),
DMA Acknowledge signals
/AS
R//W
(Required with /DS, not with /RD.)
/DS or /RD
Wait Mode
/WAIT//RDY
Acknowledge Mode
Figure 2-10. A Register Read Cycle with Multiplexed Addresses and Data
UM009402-0201