Zilog Z16C30 - Manual (Page 166)

8-11
Z16C30 USC ®
U SER ' S M ANUAL Z ILOG
UM97USC0100
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15
Reserved (Must be zero)
Bus Configuration Register (BCR) No Address (First Write after /RESET)
SepAd 16Bit
2Pulse
IACK
SRight
A
Bit(s)
Field/Bit
Name
Conditions
/Context
Description
RW
Status
Ref Chapter: Section
BCR15 SepAd 1 if AD13-8 carry register addresses WO 2: Bus Configuration Register 8-bit bus
Must be 0 16-bit bus
BCR2 16-Bit 0=8-bit data on AD7-0; 1=16-bit data on AD15-0
BCR1 2PulseIACK 0=one pulse on /PITACK per interrupt
acknowledge; 1 = two pulses (Intel compatible)
BCR0 SRightA 1=use AD6-0 as B/W, RegAddr, U/L
0=use AD7-1 Muxed AD
/PITACK
used
RW = Read/Write, RO = Read Only, WO = Write Only – for other codes see p. 8-10.
UM009402-0201