Zilog Z16C30 - Manual (Page 43)

2-17
Z16C30 USC ®
U SER ' S M ANUAL Z ILOG
UM97USC0100
Data ADnn
A//B, D//C
/CS
/SITACK
/PITACK, /WR, (/RD OR /DS),
DMA Acknowledge signals
R//W
/DS or /RD
/WAIT//RDY
(Required with /DS, not with /RD.)
Wait Mode
Acknowledge Mode
Figure 2-12. A Register Read Cycle with Non-Multiplexed Data Lines
UM009402-0201