Zilog Z80380 - Manual (Page 146)

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Z380 ™
U SER ' S M ANUAL
DC-8297-03
Z ILOG
ORW
OR (WORD)
ORW [HL,]src src = R, RX, IM, X
Operation: HL(15-0)
←
HL(15-0) OR src(15-0)
A logical OR operation is performed between the corresponding bits of the source operand
and the HL register and the result is stored in the HL register. A 1 bit is stored wherever either
of the corresponding bits in the two operands is 1; otherwise a 0 bit is stored. The contents
of the source are unaffected.
Flags: S: Set if the most significant bit of the result is set; cleared otherwise
Z: Set if all bits of the result are zero; cleared otherwise
H: Cleared
P: Set if the parity is even; cleared otherwise
N: Cleared
C: Cleared
Addressing Execute
Mode Syntax Instruction Format Time Note
R: ORW [HL,]R 11101101 101101rr 2
RX: ORW [HL,]RX 11y11101 10110111 2
IM: ORW [HL,]nn 11101101 10110110 -n(low) -n(high)- 2+r
X: ORW [HL,](XY+d) 11y11101 11110110 ——d— 4+r I
Field Encodings: rr: 00 for BC, 01 for DE, 11 for HL
y:
0 for IX, 1 for IY