Zilog Z80380 User Manual
Page 220
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Z380
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6.5.4 Interrupt Mode 3 Response for
Maskable Interrupt /INT0
(Continued)
Native (one word) or Extended mode (two words) in effect.
IEF1 and IEF2 are reset to logic 0 so as to disable further
maskable Interrupt requests. The starting address of the
service routine is fetched and loaded into the PC to resume
execution, from memory location with an address com-
posed of the I Extend contents as A31-A16 and the vector
supplied by the I/O device as A15-A0. Again the starting
address of the service routine is word-sized if the Z380
MPU is in Native mode and Long Word-sized if in the
Extended mode, in either case even-aligned, meaning
32768 different vectors can be used in the Native mode,
and 16384 different vectors can be used in the Extended
mode.
6.6 ASSIGNED INTERRUPT VECTORS MODE FOR MASKABLE INTERRUPTS /INT3-/INT1
6.7 RETI INSTRUCTION
The Z80 family I/O devices are designed to monitor the
Return from Interrupt opcodes in the instruction stream
(RETI — EDH, 4DH), signifying the end of the current
Interrupt service routine. When detected, the daisy chain
within and among the device(s) resolves and the appropri-
ate Interrupt-under-service condition clears. The Z380
MPU “reproduces” the opcode fetch transactions on the
I/O bus when the RETI instruction is executed. Note that the
Z380 MPU outputs the RETI opcodes onto both portions of
the data bus (D15-D8 and D7-D0) in the transactions.
Regardless of the Interrupt Mode in effect, interrupts on
/INT3-/INT1 is always handled by the Assigned Interrupt
Mode. This mode is similar to the interrupt handling on the
Z180’s /INT1 or /INT2 line. When the Z380 MPU recognizes
one of the external maskable Interrupts /INT3-/INT1, it
generates an Interrupt acknowledge transaction which is
different than that for /INT0. The Interrupt acknowledge
transaction for /INT3-/INT1 has the I/O bus signal /INTACK
active, with /M1 /IORQ, /IORD, and /IOWR inactive. The
interrupted PC value is pushed onto the stack. The size of
the PC value pushed onto the stack is depends on the
Native (one word) or Extended mode (two words) in effect.
IEF1 and IEF2 are reset to logic 0, disabling further maskable
Interrupt requests. The starting address of an Interrupt
service routine is fetched from a table entry and loaded into
the PC to resume execution. The address of the table entry
is composed of the I Extend contents as A31-A16, the AB
bits of the Assigned Vectors Base Register as A15-A9, and
an assigned interrupt vector specific to the request being
recognized as A8-A0. The assigned vectors are defined in
Table 6-4. If the Z380 CPU is in Extended mode, all four
bytes of the data stored in the Assigned vector location will
be used as a new PC value. If the Z380 CPU is in Native
mode, only two bytes of data from the LS Byte will be used
as a new PC value.
Table 6-4. Assigned Interrupt Vectors
Assigned
Interrupt
Interrupt
Source
Vector
/INT1
00H
/INT2
04H
/INT3
08H