Zilog Z80380 - Manual (Page 62)

5-28
Z380 ™
U SER ' S M ANUAL
DC-8297-03
Z ILOG
ANDW
AND (WORD)
ANDW [HL,]src src = R, RX, IM, X
Operation: HL(15-0)
←
HL(15-0) AND src(15-0)
A logical AND operation is performed between the corresponding bits of the source operand
and the HL register and the result is stored in the HL register. A 1 is stored wherever the
corresponding bits in the two operands are both 1s; otherwise a 0 is stored. The contents
of the source are unaffected.
Flags: S: Set if the most significant bit of the result is set; cleared otherwise
Z: Set if all bits of the result are zero; cleared otherwise
H: Set
P: Set if the parity is even; cleared otherwise
N: Cleared
C: Cleared
Addressing Execute
Mode Syntax Instruction Format Time Note
R: ANDW [HL,]R 11101101 101001rr 2
RX: ANDW [HL,]RX 11y11101 10100111 2
IM: ANDW [HL,]nn 1110110110100110 n(low)- n(high)- 2
X: ANDW [HL,](XY+d) 11y11101 11100110 ——d— 4+r I
Field Encodings: rr: 00 for BC, 01 for DE, 11 for HL
y:
0 for IX, 1 for IY